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| author |   George Stark <gnstark@sberdevices.ru> | 2023-07-21 13:23:08 +0300 |
|---|---|---|
| committer |   Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2023-07-22 18:12:53 +0100 |
| commit | 09738ccbc4148c62d6c8c4644ff4a099d57f49ad (patch) | |
| tree | c5684c6acd48c045675665ec884be63d38c19884 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | iio: core: Prevent invalid memory access when there is no parent (diff) | |
| download | wireguard-linux-09738ccbc4148c62d6c8c4644ff4a099d57f49ad.tar.xz wireguard-linux-09738ccbc4148c62d6c8c4644ff4a099d57f49ad.zip | |
iio: adc: meson: fix core clock enable/disable moment
Enable core clock at probe stage and disable it at remove stage.
Core clock is responsible for turning on/off the entire SoC module so
it should be on before the first module register is touched and be off
at very last moment.
Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Signed-off-by: George Stark <gnstark@sberdevices.ru>
Link: https://lore.kernel.org/r/20230721102413.255726-2-gnstark@sberdevices.ru
Cc: <stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions