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| author |   Sam Shih <sam.shih@mediatek.com> | 2021-12-17 20:11:46 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-01-06 18:30:54 -0800 |
| commit | 261446b2653e7b9d594f1de764691477775e2f07 (patch) | |
| tree | 07cb2d064f5bfdbe897a1b30831add48e83c38ec /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers (diff) | |
| download | wireguard-linux-261446b2653e7b9d594f1de764691477775e2f07.tar.xz wireguard-linux-261446b2653e7b9d594f1de764691477775e2f07.zip | |
dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC
This patch adds the binding documentation for topckgen, apmixedsys,
infracfg, and ethernet subsystem clocks.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211217121148.6753-2-sam.shih@mediatek.com
Reviewed-by: Ryder Lee <ryder.lee@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions