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| author |   Hugo Villeneuve <hvilleneuve@dimonoff.com> | 2023-05-29 15:35:26 -0400 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2023-06-04 20:49:12 +0800 |
| commit | 37d61885acdec51bb062cf33e0ad6fdc40114ff1 (patch) | |
| tree | f8a4628a4b238c83f8c9ffd0bbb49d574b1b5d8b /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | arm64: dts: imx8mn-var-som: add 20ms delay to ethernet regulator enable (diff) | |
| download | wireguard-linux-37d61885acdec51bb062cf33e0ad6fdc40114ff1.tar.xz wireguard-linux-37d61885acdec51bb062cf33e0ad6fdc40114ff1.zip | |
arm64: dts: imx8mn-var-som-symphony: adapt FEC pinctrl for SOMs with onboard PHY
The VAR SOM symphony carrier board can be used with SOMs which have a
soldered ethernet PHY onboard and with SOMs which don't have one.
For SOMs with an onboard PHY, the PHY on the cartrier board is not
used, and GPIO1_IO9 is used as a reset line to the onboard PHY.
For SOMs without an onboard PHY, the PHY on the carrier board is
used. For this configuration, pca9534 GPIO 5 (located on the carrier
board) is used as a reset line to the PHY, and GPIO1_IO9 is not
used.
GPIO1_IO9 is not connected to any user-accessible pins or functions,
and leaving it enabled in the mux pinctrl for both configurations is
safe.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions