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| author |   Vandita Kulkarni <vandita.kulkarni@intel.com> | 2019-05-02 20:40:59 +0530 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2019-05-14 10:36:23 +0300 |
| commit | 3c23ed13112cbce6a31b30224582169c81f1c91a (patch) | |
| tree | 22062e94dab8dd7823348c7db1ae4aa1a8696799 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/hdcp: drm_hdcp_request_srm() as static (diff) | |
| download | wireguard-linux-3c23ed13112cbce6a31b30224582169c81f1c91a.tar.xz wireguard-linux-3c23ed13112cbce6a31b30224582169c81f1c91a.zip | |
drm/i915: Fix the pipe state timing mismatch warnings
Adjust the get transcoder timings for mipi dsi as per the
set timing calculations.
v2: Use the existing intel_get_pipe_timings and do the dsi
specific adjustments in the encoder get_config hook.(Ville, Jani)
v3: Exclude VBLANK and HBLANK registers for dsi transcoder.
v4: Fix the incomplete conditional logic.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1556809862-31203-1-git-send-email-vandita.kulkarni@intel.com
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