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| author |   Horatiu Vultur <horatiu.vultur@microchip.com> | 2021-11-03 09:51:00 +0100 |
|---|---|---|
| committer |   Nicolas Ferre <nicolas.ferre@microchip.com> | 2021-12-08 11:19:20 +0100 |
| commit | 6b9f984cc86e6835880f1466faf6d60e5c51920e (patch) | |
| tree | c0b21d757e93c275c243ad4b22fbda7c73f6ca61 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | clk: gate: Add devm_clk_hw_register_gate() (diff) | |
| download | wireguard-linux-6b9f984cc86e6835880f1466faf6d60e5c51920e.tar.xz wireguard-linux-6b9f984cc86e6835880f1466faf6d60e5c51920e.zip | |
dt-bindings: clock: lan966x: Extend for clock gate support
Allow to add an optional resource to be able to access the clock gate
registers.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103085102.1656081-3-horatiu.vultur@microchip.com
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