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| author |   Richard Zhu <hongxing.zhu@nxp.com> | 2021-03-15 16:17:48 +0800 |
|---|---|---|
| committer |   Abel Vesa <abel.vesa@nxp.com> | 2021-04-04 22:39:05 +0300 |
| commit | 8304b15e132f1608973aca4527a8e12af41ddc0e (patch) | |
| tree | 9ad1122ac74a0bb51dd546747d84f2028cc3dbf1 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | clk: imx8mp: Remove the none exist pcie clocks (diff) | |
| download | wireguard-linux-8304b15e132f1608973aca4527a8e12af41ddc0e.tar.xz wireguard-linux-8304b15e132f1608973aca4527a8e12af41ddc0e.zip | |
clk: imx8mq: Correct the pcie1 sels
- The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock.
Change the sys2_pll_500m to sys2_pll_50m.
- Correct one misspell of the imx8mq_pcie1_ctrl_sels definition, from
"sys2_pll_250m" to "sys2_pll_333m".
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions