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| author |   Maxime Ripard <maxime.ripard@bootlin.com> | 2019-08-21 16:38:34 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-08-23 12:02:05 +0200 |
| commit | 89d1e51462d4749874ba3505c7de46734fda82f1 (patch) | |
| tree | 6d651558200a90a0b11e380984fd7b0612b00b75 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | arm64: dts: allwinner: h6: Add support for RTC and fix the clock tree (diff) | |
| download | wireguard-linux-89d1e51462d4749874ba3505c7de46734fda82f1.tar.xz wireguard-linux-89d1e51462d4749874ba3505c7de46734fda82f1.zip | |
ARM: dts: sunxi: Add missing watchdog interrupts
The watchdog has an interrupt on all our SoCs, but it wasn't always listed.
Add it to the devicetree where it's missing.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions