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| author |   Sunil V L <sunilvl@ventanamicro.com> | 2023-05-15 11:19:14 +0530 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-01 08:45:02 -0700 |
| commit | 8b7809e289524e02f8f0755ca632ea9e9aefbd0e (patch) | |
| tree | 8f0ff5deac7509dd2e444480f42b832436a33142 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | RISC-V: Add support to build the ACPI core (diff) | |
| download | wireguard-linux-8b7809e289524e02f8f0755ca632ea9e9aefbd0e.tar.xz wireguard-linux-8b7809e289524e02f8f0755ca632ea9e9aefbd0e.zip | |
ACPI: processor_core: RISC-V: Enable mapping processor to the hartid
processor_core needs arch-specific functions to map the ACPI ID
to the physical ID. In RISC-V platforms, hartid is the physical id
and RINTC structure in MADT provides this mapping. Add arch-specific
function to get this mapping from RINTC.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20230515054928.2079268-8-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions