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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-26 14:14:50 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-26 14:14:50 +0200 |
| commit | 9800190881cd5bc9e98c69710f04be8ae120cd38 (patch) | |
| tree | 44eeca6e9eb04ccbbf931de0bb4d3c075349577e /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | clk: renesas: r9a07g044: Add clock and reset entries for ADC (diff) | |
| parent | dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock (diff) | |
| download | wireguard-linux-9800190881cd5bc9e98c69710f04be8ae120cd38.tar.xz wireguard-linux-9800190881cd5bc9e98c69710f04be8ae120cd38.zip | |
Merge tag 'renesas-r9a07g044-dt-binding-defs-tag2' into renesas-clk-for-v5.15
Renesas RZ/G2L DT Binding Definitions Update
Missing definition for the P0_DIV2 core clock on the Renesas RZ/G2L
(R9A07G044) SoC, shared by driver and DT source files.
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