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| author |   Anup Patel <anup@brainfault.org> | 2018-12-04 15:59:51 +0530 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@sifive.com> | 2018-12-21 08:17:19 -0800 |
| commit | 9b9afe4a0ef149db2472f13d6fa3c705d2867c9c (patch) | |
| tree | 549d77afc060cc00d11c008892138ff647bfe11e /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | RISC-V: lib: minor asm cleanup (diff) | |
| download | wireguard-linux-9b9afe4a0ef149db2472f13d6fa3c705d2867c9c.tar.xz wireguard-linux-9b9afe4a0ef149db2472f13d6fa3c705d2867c9c.zip | |
RISC-V: Select GENERIC_SCHED_CLOCK for clocksource drivers
The riscv_timer driver can provide sched_clock using "rdtime"
instruction but to achieve this we require generic sched_clock
framework hence this patch selects GENERIC_SCHED_CLOCK for RISCV.
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions