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| author |   Chuanhua Han <chuanhua.han@nxp.com> | 2019-08-06 16:42:22 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2019-08-19 16:04:49 +0200 |
| commit | ced41bb1caefe4f20a03ce14fd252ba1875351da (patch) | |
| tree | 7889d66f20904549bc78b480dbdfb36f2b73b357 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | arm64: dts: ls1012a: Fix incorrect I2C clock divider (diff) | |
| download | wireguard-linux-ced41bb1caefe4f20a03ce14fd252ba1875351da.tar.xz wireguard-linux-ced41bb1caefe4f20a03ce14fd252ba1875351da.zip | |
arm64: dts: ls1028a: Fix incorrect I2C clock divider
Ls1028a platform, the i2c input clock is actually platform pll CLK / 4
(this is the hardware connection), other clock divider can not get the
correct i2c clock, resulting in the output of SCL pin clock is not
accurate.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions