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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-07-19 15:38:10 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-26 14:15:23 +0200 |
| commit | d28b1e03dc8d1070538ca3ea3f4e6732109ddf42 (patch) | |
| tree | 6f764e15316cb08aebfae30348766a06c9029f87 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | Merge tag 'renesas-r9a07g044-dt-binding-defs-tag2' into renesas-clk-for-v5.15 (diff) | |
| download | wireguard-linux-d28b1e03dc8d1070538ca3ea3f4e6732109ddf42.tar.xz wireguard-linux-d28b1e03dc8d1070538ca3ea3f4e6732109ddf42.zip | |
clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK
to R9A07G044_CLK_P0_DIV2.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719143811.2135-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions