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| author |   Anup Patel <Anup.Patel@wdc.com> | 2019-06-07 06:01:29 +0000 |
|---|---|---|
| committer |   Paul Walmsley <paul.walmsley@sifive.com> | 2019-07-01 13:24:53 -0700 |
| commit | d90d45d7dcb732f0d4fbb3b99164ae54999612d5 (patch) | |
| tree | d27cd084d87a9d5ec813eb39b4c01e6bbb587de7 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | riscv: defconfig: enable SOC_SIFIVE (diff) | |
| download | wireguard-linux-d90d45d7dcb732f0d4fbb3b99164ae54999612d5.tar.xz wireguard-linux-d90d45d7dcb732f0d4fbb3b99164ae54999612d5.zip | |
RISC-V: Fix memory reservation in setup_bootmem()
Currently, the setup_bootmem() reserves memory from RAM start to the
kernel end. This prevents us from exploring ways to use the RAM below
(or before) the kernel start hence this patch updates setup_bootmem()
to only reserve memory from the kernel start to the kernel end.
Suggested-by: Mike Rapoport <rppt@linux.ibm.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions