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| author |   Yash Shah <yash.shah@sifive.com> | 2019-07-01 16:10:30 +0530 |
|---|---|---|
| committer |   Paul Walmsley <paul.walmsley@sifive.com> | 2019-07-04 03:12:24 -0700 |
| commit | df7e9059cf6bdf4a8c11edeee30231f49815b071 (patch) | |
| tree | 6de1f04f9049f316865a4f55518e85c8d57efdfd /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | riscv: Introduce huge page support for 32/64bit kernel (diff) | |
| download | wireguard-linux-df7e9059cf6bdf4a8c11edeee30231f49815b071.tar.xz wireguard-linux-df7e9059cf6bdf4a8c11edeee30231f49815b071.zip | |
riscv: ccache: Remove unused variable
Reading the count register clears the interrupt signal. Currently, the
count registers are read into 'regval' variable but the variable is
never used. Therefore remove it. V2 of this patch add comments to
justify the readl calls without checking the return value.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions