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| author |   Ley Foon Tan <ley.foon.tan@intel.com> | 2019-02-28 18:52:50 +0800 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-03-04 12:22:03 +0000 |
| commit | 49fdbd7cfece4181b711f02b7f30fd2792700382 (patch) | |
| tree | 4dfca72ca8b81214c9359c0f39344a33240153d5 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | Linux 5.0-rc1 (diff) | |
| download | wireguard-linux-49fdbd7cfece4181b711f02b7f30fd2792700382.tar.xz wireguard-linux-49fdbd7cfece4181b711f02b7f30fd2792700382.zip | |
PCI: altera: Add Stratix 10 PCIe support
Add PCIe Root Port support for Stratix 10 device.
Main differences compared to the PCIe Root Port IP on Cyclone V
and Arria 10 devices:
- HIP interface to access Root Port configuration register
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions