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| author |   George Shen <george.shen@amd.com> | 2021-04-16 17:35:07 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-05-10 18:06:44 -0400 |
| commit | 05e62b6b6433e1159018eb5862e906a3db24dfcd (patch) | |
| tree | c35d2f0b07d1c4523c9b458113281d00785f7379 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/amd/display: remove checking sink in is_timing_changed (diff) | |
| download | wireguard-linux-05e62b6b6433e1159018eb5862e906a3db24dfcd.tar.xz wireguard-linux-05e62b6b6433e1159018eb5862e906a3db24dfcd.zip | |
drm/amd/display: Filter out YCbCr420 timing if VSC SDP not supported
[Why]
Per DP specification, YCbCr420 shall use VSC SDP.
[How]
For YCbCr420 timings, fail DP mode timing validation
if DPCD caps do not indicate VSC SDP colorimetry
support.
Signed-off-by: George Shen <george.shen@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions