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| author |   Colin Xu <colin.xu@intel.com> | 2019-02-22 14:13:42 +0800 |
|---|---|---|
| committer |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2019-05-05 17:02:25 +0800 |
| commit | 75fdb811d93c8aa4a9f73b63db032b1e6a8668ef (patch) | |
| tree | 21e4b1d6d59d68c8e7acd0807839cefb1ecf8fdc /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/i915/gvt: Revert "drm/i915/gvt: Refine the snapshort range of I915 MCHBAR to optimize gvt-g boot time" (diff) | |
| download | wireguard-linux-75fdb811d93c8aa4a9f73b63db032b1e6a8668ef.tar.xz wireguard-linux-75fdb811d93c8aa4a9f73b63db032b1e6a8668ef.zip | |
drm/i915/gvt: Add in context mmio 0x20D8 to gen9 mmio list
Depends on GEN family and I915_PARAM_HAS_CONTEXT_ISOLATION, Mesa driver
will decide whether constant buffer 0 address is relative or absolute,
and load GPU initial state by lri to context mmio INSTPM (GEN8)
or 0x20D8 (>=GEN9).
Mesa Commit fa8a764b62
("i965: Use absolute addressing for constant buffer 0 on Kernel 4.16+.")
INSTPM is already added to gen8_engine_mmio_list, but 0x20D8 is missed
in gen9_engine_mmio_list. From GVT point of view, different guest could
have different context so should switch those mmio accordingly.
v2: Update fixes commit ID.
Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch")
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
(cherry picked from commit 1e8b15a1988ed3c7429402017d589422628cdf47)
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions