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author | 2019-06-21 11:39:14 +1000 | |
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committer | 2019-06-21 11:39:15 +1000 | |
commit | 91cbf5d2365c980b0abdd0924f7fdd38bbf55c78 (patch) | |
tree | 58d69424835188c23c35e913ec795c7d458a4a81 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | Merge tag 'drm-misc-fixes-2019-06-19' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes (diff) | |
parent | drm/i915: Don't clobber M/N values during fastset check (diff) | |
download | wireguard-linux-91cbf5d2365c980b0abdd0924f7fdd38bbf55c78.tar.xz wireguard-linux-91cbf5d2365c980b0abdd0924f7fdd38bbf55c78.zip |
Merge tag 'drm-intel-fixes-2019-06-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
drm/i915 fixes for v5.2-rc6:
- GVT: Fix reserved PVINFO register write (Weinan)
- Avoid clobbering M/N values in fastset fuzzy checks (Ville)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87pnn8sbdp.fsf@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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