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| author |   Atish Patra <atish.patra@wdc.com> | 2022-02-18 16:46:52 -0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-03-21 14:58:12 -0700 |
| commit | 9dc6ce80213635cdca611d8b89f74bf010c1a8c6 (patch) | |
| tree | e28bfa5958b09599a37ba62abebb9751bccfeae4 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | RISC-V: Improve /proc/cpuinfo output for ISA extensions (diff) | |
| download | wireguard-linux-9dc6ce80213635cdca611d8b89f74bf010c1a8c6.tar.xz wireguard-linux-9dc6ce80213635cdca611d8b89f74bf010c1a8c6.zip | |
RISC-V: Remove the current perf implementation
The current perf implementation in RISC-V is not very useful as it can not
count any events other than cycle/instructions. Moreover, perf record
can not be used or the events can not be started or stopped.
Remove the implementation now for a better platform driver in future
that will implement most of the missing functionality.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions