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| author |   ShihPo Hung <shihpo.hung@sifive.com> | 2019-06-17 12:26:17 +0800 |
|---|---|---|
| committer |   Paul Walmsley <paul.walmsley@sifive.com> | 2019-06-17 03:44:44 -0700 |
| commit | bf587caae305ae3b4393077fb22c98478ee55755 (patch) | |
| tree | ab59e43380e7b8e32b79875eb26a5c27e5046957 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | riscv: dts: add initial board data for the SiFive HiFive Unleashed (diff) | |
| download | wireguard-linux-bf587caae305ae3b4393077fb22c98478ee55755.tar.xz wireguard-linux-bf587caae305ae3b4393077fb22c98478ee55755.zip | |
riscv: mm: synchronize MMU after pte change
Because RISC-V compliant implementations can cache invalid entries
in TLB, an SFENCE.VMA is necessary after changes to the page table.
This patch adds an SFENCE.vma for the vmalloc_fault path.
Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
[paul.walmsley@sifive.com: reversed tab->whitespace conversion,
wrapped comment lines]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: linux-riscv@lists.infradead.org
Cc: stable@vger.kernel.org
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions