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| author |   Justin Green <greenjustin@chromium.org> | 2023-03-09 16:06:23 -0500 |
|---|---|---|
| committer |   Chun-Kuang Hu <chunkuang.hu@kernel.org> | 2023-03-12 15:07:16 +0000 |
| commit | fb36c5020c9c9184a9a3889628a572feb69fd794 (patch) | |
| tree | 2c72aab18936b7a2091ef59aa6375c4259633919 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/mediatek: Refactor pixel format logic (diff) | |
| download | wireguard-linux-fb36c5020c9c9184a9a3889628a572feb69fd794.tar.xz wireguard-linux-fb36c5020c9c9184a9a3889628a572feb69fd794.zip | |
drm/mediatek: Add support for AR30 and BA30 overlays
Add the ability for the Mediatek DRM driver to control
the bit depth register. If the DTS indicates the device supports
10-bit overlays and the current format has a fourcc of AR30, BA30,
or RA30, we set the bit depth register to 10 bit.
The next patch in the series actually enables 10-bit overlays for
MT8195 devices, but this current patch should be a no-op. This
patch was tested by simply running Chrome on an MT8195 and looking
for regressions.
Signed-off-by: Justin Green <greenjustin@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20230309210623.1167567-1-greenjustin@chromium.org/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions