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| author |   Alexandre Torgue <alexandre.torgue@st.com> | 2022-02-03 02:59:58 +0100 |
|---|---|---|
| committer |   Alexandre Torgue <alexandre.torgue@foss.st.com> | 2022-02-25 10:53:15 +0100 |
| commit | 7a5faaee0d2e6f60897eed43366d8b541ea7882c (patch) | |
| tree | 56560f660b728482bf5a0c460b0cb641e65d1766 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ARM: dts: stm32: Add CM4 reserved memory, rproc and IPCC on DHCOR SoM (diff) | |
| download | wireguard-linux-7a5faaee0d2e6f60897eed43366d8b541ea7882c.tar.xz wireguard-linux-7a5faaee0d2e6f60897eed43366d8b541ea7882c.zip | |
ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on stm32mp157
Link between GIC and exti line is now done inside EXTI driver. So in order
to be wake up source exti irqchip has to be used.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions