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| author |   Yuantian Tang <andy.tang@nxp.com> | 2018-10-31 14:57:36 +0800 |
|---|---|---|
| committer |   Scott Wood <oss@buserror.net> | 2018-12-21 21:00:07 -0600 |
| commit | a6ee0c00a70b115e365d71eb5debcfb9de74dd1b (patch) | |
| tree | 32665ca40348bb302cbf33a48e97183ee86d3104 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | powerpc/fsl: Use new clockgen binding (diff) | |
| download | wireguard-linux-a6ee0c00a70b115e365d71eb5debcfb9de74dd1b.tar.xz wireguard-linux-a6ee0c00a70b115e365d71eb5debcfb9de74dd1b.zip | |
clk: qoriq: add more compatibles strings
Add more SoC compatible strings to support more chips.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions