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| author |   Ard Biesheuvel <ardb@kernel.org> | 2021-02-11 09:19:46 +0100 |
|---|---|---|
| committer |   Russell King <rmk+kernel@armlinux.org.uk> | 2021-03-09 10:25:17 +0000 |
| commit | c0e50736e826b51ddc437e6cf0dc68f07e4ad16b (patch) | |
| tree | 06b10b3e8e4f25d4792eb8e6e1ded3c1297fd6fa /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | ARM: 9056/1: decompressor: fix BSS size calculation for LLVM ld.lld (diff) | |
| download | wireguard-linux-c0e50736e826b51ddc437e6cf0dc68f07e4ad16b.tar.xz wireguard-linux-c0e50736e826b51ddc437e6cf0dc68f07e4ad16b.zip | |
ARM: 9057/1: cache-v7: add missing ISB after cache level selection
A write to CSSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions