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| author |   Mesih Kilinc <mesihkilinc@gmail.com> | 2018-12-02 23:23:47 +0300 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@bootlin.com> | 2018-12-04 08:41:13 +0100 |
| commit | 0380126eb9afc48d40581301bcd709f283a8148a (patch) | |
| tree | 0a76d129a0b68f47470392a7762189c81a48ffc1 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | dt-bindings: clock: Add Allwinner suniv F1C100s CCU (diff) | |
| download | wireguard-linux-0380126eb9afc48d40581301bcd709f283a8148a.tar.xz wireguard-linux-0380126eb9afc48d40581301bcd709f283a8148a.zip | |
clk: sunxi-ng: add support for suniv F1C100s SoC
The suniv F1C100s SoC (the chip in some new F-series products of
Allwinner)
has a CCU which seems to be a stripped version of the CCU in SoCs after
sun6i.
Add support for the CCU.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions