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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2020-04-28 10:06:29 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-04-28 10:06:29 +0200 |
| commit | 07ba85678145d73362e87552245aff72a88975d7 (patch) | |
| tree | 5d1b2637771d162218ab1be70f65a5d36721d6d7 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding (diff) | |
| parent | clk: renesas: Add r8a7742 CPG Core Clock Definitions (diff) | |
| download | wireguard-linux-07ba85678145d73362e87552245aff72a88975d7.tar.xz wireguard-linux-07ba85678145d73362e87552245aff72a88975d7.zip | |
Merge tag 'renesas-r8a7742-dt-binding-defs-tag' into clk-renesas-for-v5.8
Renesas RZ/G1H DT Binding Definitions
Clock and Power Domain definitions for the Renesas RZ/G1H (R8A7742) SoC,
shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions