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| author |   Peng Fan <peng.fan@nxp.com> | 2020-05-07 13:56:17 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2020-05-21 22:37:48 +0800 |
| commit | 0e40198dc28b620ead39de6e42db291418cd1183 (patch) | |
| tree | 414d38fbd1b63aa35e91353af7f9ab75740e130c /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: imx: add mux ops for i.MX8M composite clk (diff) | |
| download | wireguard-linux-0e40198dc28b620ead39de6e42db291418cd1183.tar.xz wireguard-linux-0e40198dc28b620ead39de6e42db291418cd1183.zip | |
clk: imx: add imx8m_clk_hw_composite_bus
Introduce imx8m_clk_hw_composite_bus api for bus clk root slice usage.
Because the mux switch sequence issue, we could not reuse Peripheral
Clock Slice code, need use composite specific mux operation.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions