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| author |   Hsiao Chien Sung <shawn.sung@mediatek.com> | 2024-06-20 00:38:42 +0800 |
|---|---|---|
| committer |   Chun-Kuang Hu <chunkuang.hu@kernel.org> | 2024-06-20 13:54:26 +0000 |
| commit | 231c020141cb150a59f5b28379cad82ff7bad899 (patch) | |
| tree | 73278aeeae01ebd76dc00e3ea38e0348c09fe155 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | drm/mediatek: Add missing plane settings when async update (diff) | |
| download | wireguard-linux-231c020141cb150a59f5b28379cad82ff7bad899.tar.xz wireguard-linux-231c020141cb150a59f5b28379cad82ff7bad899.zip | |
drm/mediatek: Use 8-bit alpha in ETHDR
9-bit alpha (max=0x100) is designed for special HDR related
calculation, which should be disabled by default.
Change the alpha value from 0x100 to 0xff in 8-bit form.
Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20240620-igt-v3-2-a9d62d2e2c7e@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions