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| author |   Dmitry Osipenko <digetx@gmail.com> | 2020-03-19 22:02:21 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2020-05-12 22:48:43 +0200 |
| commit | 2db2fcd7a2e3036bc4c9937c686abadb9d32524c (patch) | |
| tree | fd8edbaec76636498be4a09df7c0a4fdeecbb625 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: tegra: cclk: Add helpers for handling PLLX rate changes (diff) | |
| download | wireguard-linux-2db2fcd7a2e3036bc4c9937c686abadb9d32524c.tar.xz wireguard-linux-2db2fcd7a2e3036bc4c9937c686abadb9d32524c.zip | |
clk: tegra20: Use custom CCLK implementation
We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK
intermediate re-parenting will be performed by the clock driver. There is
now special CCLK implementation that supports all CCLK quirks, this patch
makes Tegra20 SoCs to use that implementation.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions