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| author |   Colin Ian King <colin.king@canonical.com> | 2021-04-20 15:29:07 +0100 |
|---|---|---|
| committer |   Peter Zijlstra <peterz@infradead.org> | 2021-04-23 09:03:15 +0200 |
| commit | 32d35c4a96ec79446f0d7be308a6eb248b507a0b (patch) | |
| tree | dc4f860f1d72b99aa639e93676ae258a15b44d30 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | perf/x86/rapl: Add support for Intel Alder Lake (diff) | |
| download | wireguard-linux-32d35c4a96ec79446f0d7be308a6eb248b507a0b.tar.xz wireguard-linux-32d35c4a96ec79446f0d7be308a6eb248b507a0b.zip | |
perf/x86: Allow for 8<num_fixed_counters<16
The 64 bit value read from MSR_ARCH_PERFMON_FIXED_CTR_CTRL is being
bit-wise masked with the value (0x03 << i*4). However, the shifted value
is evaluated using 32 bit arithmetic, so will UB when i > 8. Fix this
by making 0x03 a ULL so that the shift is performed using 64 bit
arithmetic.
This makes the arithmetic internally consistent and preparers for the
day when hardware provides 8<num_fixed_counters<16.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20210420142907.382417-1-colin.king@canonical.com
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions