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| author |   Oleksij Rempel <o.rempel@pengutronix.de> | 2023-01-31 09:46:42 +0100 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2023-03-06 10:01:47 +0800 |
| commit | 37c24ed660e4ddaa1a562c75b158128a5515571e (patch) | |
| tree | ad19251fe3315fe8a27e016e24e07cfa9ed3ee40 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | ARM: dts: imx6ul: set enet_clk_ref to CLK_ENETx_REF_SEL (diff) | |
| download | wireguard-linux-37c24ed660e4ddaa1a562c75b158128a5515571e.tar.xz wireguard-linux-37c24ed660e4ddaa1a562c75b158128a5515571e.zip | |
ARM: dts: imx6ul-prti6g: configure ethernet reference clock parent
On this board the PHY is the ref clock provider. So, configure ethernet
reference clock as input.
Without this patch we have relatively high amount of dropped packets.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions