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author | 2019-02-27 15:18:08 +0800 | |
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committer | 2019-03-20 23:39:48 -0500 | |
commit | 3d5cc272319d6b7bf2e7d8aa9b1c3b0fe3e85b3f (patch) | |
tree | ef40d2d2d0b87f354b588b236d0ae8bfff142ec7 /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | drm/amd/display: 3.2.22 (diff) | |
download | wireguard-linux-3d5cc272319d6b7bf2e7d8aa9b1c3b0fe3e85b3f.tar.xz wireguard-linux-3d5cc272319d6b7bf2e7d8aa9b1c3b0fe3e85b3f.zip |
drm/amd/display: Programming correct VRR_EN bit in VTEM structure
[Why]
In HDMI plugfest, MTK report our EMP with VRR_EN bit = 0.
VRR_EN bit is EMP-MD0-bit 0. Currently driver set 1 to bit 3.
[How]
Programming correct VRR_EN bit in EMP-MD0-bit0.
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Reza Amini <Reza.Amini@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions