diff options
| author |   Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2025-01-07 17:01:26 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-21 16:22:59 +0100 |
| commit | 51786c8b47edfce3cee6eef9c8a62a035f9fbead (patch) | |
| tree | 7713dae3ba2676e528c26dd11dfac11cb0a46bf1 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | arm64: dts: renesas: r8a77990: Re-add voltages to OPP table (diff) | |
| download | wireguard-linux-51786c8b47edfce3cee6eef9c8a62a035f9fbead.tar.xz wireguard-linux-51786c8b47edfce3cee6eef9c8a62a035f9fbead.zip | |
arm64: dts: renesas: r8a779h0: Remove #address- and #size-cells from AVB[0-2]
When describing the PHYs connected to AVB1 and AVB2, mdio nodes will be
needed to describe the connections, and each mdio node will need to
contain these two properties instead. This will make the #address-cells
and #size-cells described in the base SoC include file redundant and
they will produce warnings, remove them.
In an effort to keep all three AVB nodes style consistent add an mdio
node to AVB0 already described and rename the phy node to better
describe the PHY that is connected to AVB0 before adding more PHYs.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250107160127.528933-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions