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| author |   Peng Fan <peng.fan@nxp.com> | 2020-05-07 13:56:13 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2020-05-20 09:26:45 +0800 |
| commit | 77f5d2d97353149d43b401ae98bd0c071cdd2fb6 (patch) | |
| tree | cccab20da23396fc269ff1f3521ce59c0e58793a /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: imx: imx8mp: fix pll mux bit (diff) | |
| download | wireguard-linux-77f5d2d97353149d43b401ae98bd0c071cdd2fb6.tar.xz wireguard-linux-77f5d2d97353149d43b401ae98bd0c071cdd2fb6.zip | |
clk: imx8mp: Define gates for pll1/2 fixed dividers
Inspried from
commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers")
On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.
Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions