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| author |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-12-18 11:53:56 +0100 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2025-02-13 12:01:32 +0100 |
| commit | 79214284ac58127141f3d317603648993376ef44 (patch) | |
| tree | db68b75cd55bc1eeec323c31bb7192ab05e55dbc /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | arm64: dts: mediatek: mt8188: Assign apll1 clock as parent to avoid hang (diff) | |
| download | wireguard-linux-79214284ac58127141f3d317603648993376ef44.tar.xz wireguard-linux-79214284ac58127141f3d317603648993376ef44.zip | |
arm64: dts: mediatek: mt8188: Add VDO0's DSC and MERGE block nodes
Add nodes for the DSC0 and MERGE0 blocks, located in VDOSYS0 and
necessary to add support for Display Stream Compression with a
display pipeline that looks like:
[other components] -> DSC0 -> MERGE0 -> Display Interface
Link: https://lore.kernel.org/r/20241218105356.39111-1-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions