diff options
| author |   Charlene Liu <charlene.liu@amd.com> | 2019-03-01 11:12:50 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-03-20 23:39:48 -0500 |
| commit | 7fe538a4d64135d8f8e4aca8d0aedf266958025c (patch) | |
| tree | 4acc1d7a90038a20cf4b823e7e5d5b5fe2b8927d /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | drm/amd/display: Fix setting DP_VID_N_MUL (diff) | |
| download | wireguard-linux-7fe538a4d64135d8f8e4aca8d0aedf266958025c.tar.xz wireguard-linux-7fe538a4d64135d8f8e4aca8d0aedf266958025c.zip | |
drm/amd/display: fix DP 422 VID_M half the rate issue.
[Description]
when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N.
for YCbCr420 or compressed YCbCr422, using half rate as YCbCr444.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions