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| author |   Oleksij Rempel <o.rempel@pengutronix.de> | 2023-01-31 09:46:40 +0100 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2023-03-06 10:01:46 +0800 |
| commit | 8940c105273fcde00a60023f68f8a5b75e1df0cc (patch) | |
| tree | 4517ec612cd97eae8f049599875641b1a449355a /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | ARM: dts: imx6dl-eckelmann-ci4x10: configure ethernet reference clock parent (diff) | |
| download | wireguard-linux-8940c105273fcde00a60023f68f8a5b75e1df0cc.tar.xz wireguard-linux-8940c105273fcde00a60023f68f8a5b75e1df0cc.zip | |
ARM: dts: imx6ul: set enet_clk_ref to CLK_ENETx_REF_SEL
IMX6UL_CLK_ENETx_REF is behind of CLK_ENETx_REF_SEL:
FEC MAC <---------- CLK_ENETx_REF_SEL <--------- CLK_ENETx_REF
\
^------<-> CLK_ENETx_REF_PAD
We should point to the clock selector instead. So, we will be able to
use external clock source from CLK_ENETx_REF_PAD as well.
At same time, remove enet_out clk. It is using always the same clock as
enet_clk_ref and do not help to solve any challenges of this HW.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions