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| author |   Joseph Lo <josephl@nvidia.com> | 2019-05-29 16:21:33 +0800 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2020-05-12 22:48:41 +0200 |
| commit | cd4d6f357545bc03112265b19e5ed50592812986 (patch) | |
| tree | c5c1e23047f2282d4b60353255a367d6b040964b /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: tegra: Rename Tegra124 EMC clock source file (diff) | |
| download | wireguard-linux-cd4d6f357545bc03112265b19e5ed50592812986.tar.xz wireguard-linux-cd4d6f357545bc03112265b19e5ed50592812986.zip | |
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
clock source.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions