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| author |   Adam Ford <aford173@gmail.com> | 2020-04-04 11:15:36 -0500 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2020-05-30 12:28:51 -0700 |
| commit | d63ed4ff41bb2d1f0738f801bcd9ff60dfc1eb7f (patch) | |
| tree | aac8750bd33b516d83fbc577f09706d1ee6bd2a5 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: vc5: Add support for IDT VersaClock 5P49V6965 (diff) | |
| download | wireguard-linux-d63ed4ff41bb2d1f0738f801bcd9ff60dfc1eb7f.tar.xz wireguard-linux-d63ed4ff41bb2d1f0738f801bcd9ff60dfc1eb7f.zip | |
dt: Add bindings for IDT VersaClock 5P49V5925
IDT VersaClock 5 5P49V6965 has 5 clock outputs, 4 fractional dividers.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lkml.kernel.org/r/20200404161537.2312297-2-aford173@gmail.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions