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| author |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2025-02-13 12:20:08 +0100 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2025-03-06 10:53:06 +0100 |
| commit | e913aec7ed80407a8068bdc0a88c426e1c9e5206 (patch) | |
| tree | c12346aa66c5bc4beb3abb52d51b1a89153a9c07 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays (diff) | |
| download | wireguard-linux-e913aec7ed80407a8068bdc0a88c426e1c9e5206.tar.xz wireguard-linux-e913aec7ed80407a8068bdc0a88c426e1c9e5206.zip | |
arm64: dts: mediatek: mt8395-nio-12l: Preconfigure DSI0 pipeline
This board can use a MIPI-DSI panel on the DSI0 connector: in
preparation for adding an overlay for the Radxa Display 8HD,
add a pipeline connecting VDOSYS0 components to DSI0.
This pipeline remains disabled by default, as it is expected
to be enabled only by a devicetree overlay that declares the
actual DSI panel node, completing the graph.
Link: https://lore.kernel.org/r/20250213112008.56394-4-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions