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author | 2024-10-01 14:50:54 +0100 | |
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committer | 2024-10-01 14:50:54 +0100 | |
commit | d8bd6313e83d0603751d4241941008d5fff3ae25 (patch) | |
tree | 3940a27e41b2b3789949e7ef732772775d6ad70b /tools/perf/scripts/python/gecko.py | |
parent | ASoC: rt1320: fix the range of patch code address (diff) | |
parent | ASoC: fsl_micfil: Enable micfil error interrupt (diff) | |
download | wireguard-linux-d8bd6313e83d0603751d4241941008d5fff3ae25.tar.xz wireguard-linux-d8bd6313e83d0603751d4241941008d5fff3ae25.zip |
ASoC: fsl_micfil: fix and improvement
Merge series from Shengjiu Wang <shengjiu.wang@nxp.com>:
Fix the usage of regmap_write_bits().
Move mclk clock enablement to late stage.
Enable the micfil error interrupt.
Diffstat (limited to 'tools/perf/scripts/python/gecko.py')
0 files changed, 0 insertions, 0 deletions