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| author |   Yevgeny Kliteynik <kliteyn@nvidia.com> | 2021-02-06 22:11:52 +0200 |
|---|---|---|
| committer |   Saeed Mahameed <saeedm@nvidia.com> | 2021-03-10 11:01:59 -0800 |
| commit | 84076c4c800d1be77199a139d65b8b136a61422e (patch) | |
| tree | 329ff714ad0ff8d129da485c7b6a46e3a771d732 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | net/mlx5: SF: Fix error flow of SFs allocation flow (diff) | |
| download | wireguard-linux-84076c4c800d1be77199a139d65b8b136a61422e.tar.xz wireguard-linux-84076c4c800d1be77199a139d65b8b136a61422e.zip | |
net/mlx5: DR, Fix potential shift wrapping of 32-bit value in STEv1 getter
Fix 32-bit variable shift wrapping in dr_ste_v1_get_miss_addr.
Fixes: a6098129c781 ("net/mlx5: DR, Add STEv1 setters and getters")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions