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| author |   Shengjiu Wang <shengjiu.wang@nxp.com> | 2024-09-27 16:00:30 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2024-09-30 01:09:29 +0200 |
| commit | b47024dc624bcffb89d238f4a5b490363cea2a1e (patch) | |
| tree | 0443086cb6e6eb38a2d7983646bd241f253b9c31 /tools/perf/scripts/python/parallel-perf.py | |
| parent | ASoC: fsl_micfil: fix regmap_write_bits usage (diff) | |
| download | wireguard-linux-b47024dc624bcffb89d238f4a5b490363cea2a1e.tar.xz wireguard-linux-b47024dc624bcffb89d238f4a5b490363cea2a1e.zip | |
ASoC: fsl_micfil: Add mclk enable flag
Previously the mclk is enabled in probe() stage, which
is not necessary. Move mclk enablement to hw_params()
and mclk disablement to hw_free() will be more efficient.
'mclk_flag' is used for this case.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://patch.msgid.link/1727424031-19551-3-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions