diff options
| author |   Eric Anholt <eric@anholt.net> | 2011-11-07 16:07:05 -0800 |
|---|---|---|
| committer |   Keith Packard <keithp@keithp.com> | 2011-11-07 19:29:36 -0800 |
| commit | 9ca1d10d748e56964de95e3ed80211b192f56cf4 (patch) | |
| tree | d19e64f9d226ca49c6b10608f62c4c30efd3d7aa /tools/perf/scripts/python/sched-migration.py | |
| parent | drm/i915: Turn on a required 3D clock gating bit on Sandybridge. (diff) | |
| download | wireguard-linux-9ca1d10d748e56964de95e3ed80211b192f56cf4.tar.xz wireguard-linux-9ca1d10d748e56964de95e3ed80211b192f56cf4.zip | |
drm/i915: Turn on another required clock gating bit on gen6.
Unlike the previous one, I don't have known testcases it fixes. I'd
rather not go through the same debug cycle on whatever testcases those
might be.
Signed-off-by: Eric Anholt <eric@anholt.net>
Cc: stable@kernel.org
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions