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| author |   Rhyland Klein <rklein@nvidia.com> | 2016-01-14 14:24:37 -0500 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2016-02-02 15:49:26 +0100 |
| commit | fd2963b071c1346572285a274a6ae8f26a970c4d (patch) | |
| tree | bdc7652551379221c049a13f595ec97db81adff6 /tools/perf/scripts/python/sched-migration.py | |
| parent | clk: tegra: Do not disable PLLE when under hardware control (diff) | |
| download | wireguard-linux-fd2963b071c1346572285a274a6ae8f26a970c4d.tar.xz wireguard-linux-fd2963b071c1346572285a274a6ae8f26a970c4d.zip | |
clk: tegra: Fix typos around clearing PLLE bits during enable
While enabling PLLE on both Tegra114 and Tegra210, we should be clearing
PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting
them. This patch fixes both places where we incorrectly set instead of
cleared those bits.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions