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| author |   Steven J. Hill <sjhill@mips.com> | 2012-07-12 17:21:31 +0000 |
|---|---|---|
| committer | Steven J. Hill <sjhill@mips.com> | 2012-09-13 15:43:53 -0500 |
| commit | e6de1a09a2f6a6825341e8463866553b77848ed6 (patch) | |
| tree | 473dbf84055f232628e0b37ecfd4d9244d500eb5 /tools/perf/scripts/python/sctop.py | |
| parent | MIPS: Avoid pipeline stalls on some MIPS32R2 cores. (diff) | |
| download | wireguard-linux-e6de1a09a2f6a6825341e8463866553b77848ed6.tar.xz wireguard-linux-e6de1a09a2f6a6825341e8463866553b77848ed6.zip | |
MIPS: uasm: Add INS and EXT instructions.
These are MIPS32R2 instructions for merging and extracting bit fields
from one GPR into another.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Diffstat (limited to 'tools/perf/scripts/python/sctop.py')
0 files changed, 0 insertions, 0 deletions