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| author |   Tony Lindgren <tony@atomide.com> | 2024-03-27 09:10:37 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2024-04-10 09:15:40 +0300 |
| commit | a0a621533fe796d5a92ece5573663cb25bec470c (patch) | |
| tree | ffe1f50b2cc4403af716e8a1b1c1ecf9ae14578e /tools/perf/scripts/python/stackcollapse.py | |
| parent | ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP (diff) | |
| download | wireguard-linux-a0a621533fe796d5a92ece5573663cb25bec470c.tar.xz wireguard-linux-a0a621533fe796d5a92ece5573663cb25bec470c.zip | |
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
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