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| author |   Linus Walleij <linus.walleij@linaro.org> | 2018-07-12 14:52:00 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2018-09-20 15:03:25 -0700 |
| commit | 3be9349f38c7dd7f108a71f640908a727101d2db (patch) | |
| tree | 675e133fbc1b3999e8a7afdb40a964c53e733fc8 /tools/perf/scripts/python/stackcollapse.py | |
| parent | arm: dts: ste: Update coresight bindings for hardware port (diff) | |
| download | wireguard-linux-3be9349f38c7dd7f108a71f640908a727101d2db.tar.xz wireguard-linux-3be9349f38c7dd7f108a71f640908a727101d2db.zip | |
ARM: dts: ux500: Mark PRCMU as syscon compatible
We need to distribute out the responsibilities of the PRCMU
registers instead of having one big lump handling everything.
By making it syscon compatible, we can start grabbing the
register map elsewhere when needed.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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