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| author |   Peter Ujfalusi <peter.ujfalusi@ti.com> | 2016-04-10 13:20:09 -0600 |
|---|---|---|
| committer |   Paul Walmsley <paul@pwsan.com> | 2016-04-10 13:20:09 -0600 |
| commit | 9ad4d9a38a7f62a4891124501cdce4e768dbba16 (patch) | |
| tree | 78163137670d453423d1d40540a8d6de1310dc08 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ARM: DRA7: clockdomain: Implement timer workaround for errata i874 (diff) | |
| download | wireguard-linux-9ad4d9a38a7f62a4891124501cdce4e768dbba16.tar.xz wireguard-linux-9ad4d9a38a7f62a4891124501cdce4e768dbba16.zip | |
ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8
Add missing data for all McASP ports for the dra7 family
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions