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| author |   Vignesh R <vigneshr@ti.com> | 2016-04-10 13:20:09 -0600 |
|---|---|---|
| committer |   Paul Walmsley <paul@pwsan.com> | 2016-04-10 13:20:09 -0600 |
| commit | b05ff3c394bc5dbb1bc88073759f01c0ebdf5de1 (patch) | |
| tree | a06545ba9c99eb64c6199002809ccee89e200399 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 (diff) | |
| download | wireguard-linux-b05ff3c394bc5dbb1bc88073759f01c0ebdf5de1.tar.xz wireguard-linux-b05ff3c394bc5dbb1bc88073759f01c0ebdf5de1.zip | |
ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS
Add hwmod entries for the PWMSS on DRA7.
Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock
equal to L4PER2_L3_GICLK/2(l3_iclk_div/2).
Signed-off-by: Vignesh R <vigneshr@ti.com>
[fcooper@ti.com: Do not add eQEP, ePWM and eCAP hwmod entries]
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
[paul@pwsan.com: fixed sparse warnings; added missing comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions